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XRD9855/9856 XRD98L55/98L56
CCD Image Digitizers with CDS, PGA and 10-Bit A/D
July 2001
FEATURES
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10-Bit Resolution ADC 18 - 27MHz Maximum Sampling Rate Correlated Double Sampling (CDS) Programmable Gain from 6dB to 38dB (PGA) Digitally Controlled Analog Offset-Calibration CCD Black Level Offset Compensation at Frame Rate CDS Clocks Sample Rising Edge or Falling Edge Single 5V or 3V Power Supply Low Power for Battery Applications: XRD9855/56: XRD98L55/L56:
250/ 300m W @ V DD = 5.0V
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3-State Digital Outputs ESD Protection to Over 2000V
APPLICATIONS
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Digital Video Camcorders Digital Still Cameras PC Video Teleconferencing Digital Copiers Infrared Image Digitizers CCD/CIS Imager Interface CCTV/Security Camera 2D Bar Code Readers Industrial Cameras
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120/150mW @ VDD = 3.0V
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50A-Typ Current in Stand By Mode
GENERAL DESCRIPTION The XRD9855/XRD9856 are complete CCD Image Digitizers for digital cameras. The products include a high bandwidth differential Correlated Double Sampler (CDS), 8-bit digitally Programmable Gain Amplifier (PGA), 10-bit Analog-to-Digital Converter (ADC) and digital controlled black level auto-calibration circuitry.
The C or el ed D oubl Sam pl ( D S ) subt act t r at e er C r s he C C D out put si gnal bl ack l evel fom t vi r he deo l evel . C om m on m ode si gnal se and pow ersuppl noi ar noi y se e r ect by t dif ental D S i ej ed he fer i C nputst age.C D S i nput s ar desi e gned t be used eiher dif entalor si eo t fer i ngl ended. The aut calbr i cicui com pensat f any i er o i aton r t es or nt nalofsetoft X R D 9855/ R D 9856 as w el as bl f he X l ack l evelofsetf om t C C D . f r he
The PGA is digitally controlled with 8-bit resolution on a linear dB scale, resulting in a gain range of 6dB to 38dB with 0.125dB per LSB of the gain code. The PGA and black level auto-calibration are controlled through a simple 3-wire serial interface. The timing circuitry is designed to enable users to select a wide variety of available CCD and image sensors for their applications. The XRD9855/XRD9856 has direct access to the PGA output and ADC input through the pin TESTVIN. The XRD9855/XRD9856 are packaged in 48-lead surface mount TQFP to reduce space and weight, and suitable for hand-held and portable applications.
ORDERING INFORMATION
Part No. XRD9855AIV XRD98L55AIV XRD9856AIV XRD98L56AIV Package 48 Lead TQFP (7 x 7 x 1.4 mm) 48 Lead TQFP (7 x 7 x 1.4 mm) 48 Lead TQFP (7 x 7 x 1.4 mm) 48 Lead TQFP (7 x 7 x 1.4 mm) Operating Temperature Range Power Supply -40C to 85C -40C to 85C -40C to 85C -40C to 85C 5.0V 3.0V 5.0V 3.0V Maximum Sampling Rate 18 MSPS 18 MSPS 27 MSPS 27 MSPS
Rev. 1.01
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRD9855/9856 XRD98L55/98L56
VDD GND VRBO VRB TESTVIN VRT VRTO VDD DVDD In_Pos CDS In_Neg DGND SHD SHP RSTCCD CLAMP CLK_POL Timing Generator SYNC OVER Offset Calibration Serial Port Registers UNDER PGA ADC Reg DB[9:0]
SCLK SDI LOAD
GND
STBY1 STBY2
RESET
EnableCal
OE
Figure 1. XRD9855/XRD9856 Simplified Block Diagram
Rev. 1.01
2
XRD9855/9856 XRD98L55/98L56
NC V RB V RBO GND In_Pos In_Neg V DD V RTO V RT SDI LOAD NC 36 CLAMP SHD SHP RSTCCD GND CLK_POL VDD SYNC UNDER DB0 DB1 NC 37 25 24
PIN CONFIGURATION
48 1 12
13
SCLK RESET STBY2 STBY1 Test GND EnableCal VDD OE OVER DB9 DB8
48 Lead TQFP (7 x 7 x 1.0 mm)
PIN DESCRIPTION - 48 pin TQFP
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Symbol NC NC DB2 DB3 DB4 DGND DVDD DB5 DB6 DB7 NC NC DB8 DB9 OVER Description No Connect. No Connect. ADC Output. DB0 is the LSB, DB9 is the MSB. ADC Output. ADC Output. Digital Output Ground. Digital Output Power Supply. Must be less than or equal to VDD. ADC Output. ADC Output. ADC Output. No Connect. No Connect. ADC Output. ADC Output. MSB Over Range Output Bit. OVER goes high to indicate the ADC input voltage is greater than VRT.
Rev. 1.01
3
NC NC DB2 DB3 DB4 DGND DV DD DB5 DB6 DB7 NC NC
XRD9855/9856 XRD98L55/98L56
PIN DESCRIPTION - 48 pin TQFP (CONT'D)
Pin # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol OE VDD EnableCal GND TESTVIN STBY1 STBY2 RESET SCLK NC LOAD SDI VRT VRTO VDD In_Neg In_Pos GND V RBO V RB NC CLAMP SHD SHP RSTCCD GND CLK_POL VDD SYNC UNDER DBO DB1 NC Description Digital Output Enable (Three-State Control). Pull OE low to enable output drivers. Pull OE high to put output drivers in high impedance state. Analog Power Supply. Calibration Enable. Automatic offset calibration control. Analog Ground. ADC Test Input & PGA Test Output. Standby Control 1. Pull low to put chip in power down mode. Standby Control 2. Short to STBY1 pin if not using TESTVIN pin. Chip Reset. Pull high to reset all internal registers. Shift Clock. Shift register latches SDI data on rising edges of SCLK. No Connect. Data Load. Rising edge loads data from shift register to internal register. Load must be low to enable shift register. Serial Data Input. Top ADC Reference. Voltage at VRT sets full-scale of ADC. Internal Bias for VRT. Short VRT to VRTO to use internal reference voltage. Analog Power Supply. CDS Inverting Input. Connect via capacitor to CCD video output. CDS Non-inverting Input. Connect via capacitor to CCD supply. Analog Ground. Internal Bias for VRB. Short VRB to VRB0 to use internal reference voltage. Bottom ADC Reference. Voltage at VRB sets zero scale of the ADC. No Connect. CDS DC Restore Clamp. Clamps In_Pos & In_Neg to internal bias voltage. CDS Clock. Controls sampling of the pixel video level. CDS Clock. Controls sampling of the pixel black level. CCD Reset Pulse Disconnect. Used to decouple CDS during the reset pulse. Analog Ground. Clock Polarity. Controls the polarity of SHP, SHD & CLAMP. Analog Power Supply. Digital output for Exar test purposes only. No connect. Under Range Output Bit. UNDER goes high to indicate the ADC input voltage is less than VRB. ADC Output. LSB ADC Output. No Connect.
Rev. 1.01
4
XRD9855/9856 XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS - XRD9855 and XRD9856 Unl ess ot herw i speci i se f ed: D V DD = VDD = 5.0V, Pixel Rate = 18MSPS, VRT = 3.8V, VRB = 0.5V
Symbol Parameter Min. Typ. Max. Unit Conditions
CDS Performance CDSVIN BW SR FT Input Range Small Signal Bandwidth (-3dB) Slew Rate Feed-through (Hold Mode) 200 60 40 -60 800 mV PP MHz V/s dB 400mV Step Input Pixel (Black Level - Video Level)
PGA Parameters AVMIN AVMAX PGA n GE Minimum Gain Maximum Gain Resolution Gain Error 3.5 35.5 5 37 8 5 6.5 38.5 dB dB bits % FS Transfer function is linear steps in dB (1LSB = 0.125dB) At maximum or minimum gain setting
ADC Parameters (Measured Through TESTVIN) ADC n fs DNL Resolution Max Sample Rate Differential Non-Linearity 10 27 -1 +0.75 1.2 bits MSPS LSB Up to 18MHz sample rate (XRD9855) DNL27 Differential Non-Linearity -1 +1.3 2.0 LSB Up to 27MHz sample rate (XRD9856) EZS EFS VIN Zero Scale Error Full Scale Error DC Input Range GND -50 50 4 VDD mV % FS V VIN of the ADC can swing from GND to VDD. Input range is limited by the output swing of the PGA VRT >VRB VRT >VRB Measured relative to VRB
VRT V RB VREF RL V RB VRT
Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Ladder Resistance
1.5 0.3 1.0 280
3.8 0.5 3.3 400
VDD VDD-1 VDD 520
V V V Ohms
Self Bias VRB Self Bias VRT
( (
VRB = VDD 10 VRT = VDD 1.30
) )
0.4
0.5
0.6
V
VRB connected to VRBO VRT connected to VRTO
3.5
3.8
4.1
V
Rev. 1.01
5
XRD9855/9856 XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS - XRD9855 and XRD9856 (CONT'D) Unless otherwise specified: DVDD = VDD = 5.0V, Pixel Rate = 18MSPS, VRT = 3.8V, VRB = 0.5V
Symbol Parameter Min. Typ. Max. Unit Conditions
System Specifications DNL S DNL S27 INLSMIN INL SMAX VOS
MINAV
System DNL System DNL 27 MSPS INL @ Minimum Gain INL @ Maximum Gain Offset (Input Referred) @ Minimum Gain
1.0 1.0
LSB LSB LSB LSB
XRD9855 up to 18 MSPS XRD9856 up to 27 MSPS INL error is dominated by CDS/PGA linearity. INL error is dominated by CDS/PGA linearity. Offset is defined as the input pixel value-0.5 LSB required to cause the ADC output to switch from "Zero scale" to "Zero scale + 1LSB". Offset is measured after calibration. Zero scale is the code in the offset register. Offset depends on PGA gain code. Noise depends upon gain setting of the PGA. Noise depends upon gain setting of the PGA.
5
mV
VOS
MAXAV
Offset (Input Referred) @ Maximum Gain Input Referred Noise @ Maximum Gain Input Referred Noise @ Minimum Gain
1
mV
en en
MAXAV
0.2 1.1
mVrms mVrms
MINAV
Digital Inputs VIH V IL IL C IN Digital Outputs VOH V OL IOZ Digital Output High Voltage Digital Output Low Voltage High-Z Leakage -10 DVDD-0.5 0.5 10 V V A While sourcing 2mA. While sinking 2mA. OE=1 or STBY1= STBY2 = 0. Output between GND & DVDD. Digital Input High Voltage Digital Input Low Voltage DC Leakage Current Input Capacitance 5 5 2.0 0.7 V V A pF Input Between GND and VDD.
Rev. 1.01
6
XRD9855/9856 XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS - XRD9855 and XRD9856 (CONT'D) Unless otherwise specified: DVDD = VDD = 5.0V, Pixel Rate = 18MSPS, VRT = 3.8V, VRB = 0.5V
Symbol Parameter Min. Typ. Max. Unit Conditions
Digital I/O Timing TDL TPW1 TPW2 TPIX T BK TVD TRST TSC TSET Latency Power Supplies VDD DVDD IDD IDD27 IDDPD Analog Supply Voltage Digital Output Supply Voltage Supply Current Supply Current @ 27MHz Power Down Supply Current 4.5 2.7 5.0 5.0 50 55 50 5.5 5.5 75 85 100 V V mA mA A DVDD < VDD Always DVDD = VDD = 5.0V (XRD9855) FS = 27MHz (XRD9856) STBY1 = 0 and STBY2 = 0 Data Valid Delay Pulse Width of SHD Pulse Width of SHD Pixel Period Sample Black Aperture Delay 10 10 37 56 6 20 25 ns ns ns ns ns VDD = 4.5V to 5.5V, Temperature -40C to 85C range Sample Video Aperture Delay 5 ns VDD = 4.5V to 5.5V, Temperature -40C to 85C range RSTCCD Switch Delay 0 4 ns VDD = 4.5V to 5.5V, Temperature -40C to 85C range Shift Clock Period Shift Register Setup Time Pipeline Delay 50 10 4 100 ns ns cycles
Rev. 1.01
7
XRD9855/9856 XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS - XRD98L55 and XRD98L56 Unless otherwise specified: DVDD = VDD = 2.7V, Pixel Rate = 18MSPS, VRT = 2.07V, VRB = 0.27V
Symbol Parameter Min. Typ. Max. Unit Conditions
CDS Performance CDSVIN BW SR FT Input Range Small Signal Bandwidth (-3dB) Slew Rate Feed-through (Hold Mode) 200 60 40 -60 800 mV PP MHz V/s dB 400mV Step Input Pixel (Black Level - Video Level)
PGA Parameters AVMIN AVMAX PGA n GE Minimum Gain Maximum Gain Resolution Gain Error 3.5 36.5 5 37 8 5 6.5 38.5 dB dB bits % FS Transfer function is linear steps in dB (1LSB = 0.125dB) At maximum or minimum gain setting
ADC Parameters (Measured Through TESTVIN) ADC n fs DNL Resolution Max Sample Rate Differential Non-Linearity 10 27 -1 +0.75 1.2 bits MSPS LSB Up to 18MHz sample rate (XRD98L55) DNL27 Differential Non-Linearity -1 +1.3 2.0 LSB Up to 27MHz sample rate (XRD98L56) EZS EFS VIN Zero Scale Error Full Scale Error DC Input Range GND -50 50 4 VDD mV % FS V VIN of the ADC can swing from GND to VDD. Input range is limited by the output swing of the PGA VRT >VRB VRT >VRB Measured relative to VRB
VRT V RB VREF RL V RB VRT
Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Ladder Resistance
1.2 0.2 1.0 280
2.07
VDD VDD 520
V V V Ohms
0.27 VDD-1 1.8 400
Self Bias VRB Self Bias VRT
( (
VRB = VDD 10
VRT = VDD 1.30
) )
0.20
0.30
0.40
V
VRB connected to VRBO VRT connected to VRTO. TPW2
2.0
2.3
2.6
V
Rev. 1.01
8
XRD9855/9856 XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS - XRD98L55 and XRD98L56 (CONT'D) Unless otherwise specified: DVDD = VDD = 2.7V, Pixel Rate = 18MSPS, VRT = 2.7V, VRB = 0.27V
Symbol Parameter Min. Typ. Max. Unit Conditions
System Specifications DNL S DNL S27 INLSMIN INL SMAX VOS
MINAV
System DNL System DNL 27 MSPS INL @ Minimum Gain INL @ Maximum Gain Offset (Input Referred) @ Minimum Gain
1.0 1.5 2 2 5
LSB LSB LSB LSB mV
XRD98L55 up to 18 MSPS XRD98L56 up to 27 MSPS INL error is dominated by CDS/PGA linearity. INL error is dominated by CDS/PGA linearity. Offset is defined as the input pixel value -0.5 LSB required to cause the ADC output to switch from "Zero scale" to "Zero scale + 1LSB". Offset is measured after calibration.
VOS
MAXAV
Offset (Input Referred) @ Maximum Gain
1
mV
Zero scale is the code in the offset register. Offset depends on PGA gain code.
en en
MAXAV
Input Referred Noise @ Maximum Gain Input Referred Noise @ Minimum Gain
0.2 0.7
mVrms mVrms
Noise depends upon gain setting of the PGA. Noise depends upon gain setting of the PGA.
MINAV
Digital Inputs VIH V IL IL C IN Digital Outputs VOH V OL IOZ Digital Output High Voltage Digital Output Low Voltage High-Z Leakage -10 DVDD-0.5 0.5 10 V V A While sourcing 2mA. While sinking 2mA. OE=1 or STBY1= STBY2 = 0. Output between GND & DVDD. Digital Input High Voltage Digital Input Low Voltage DC Leakage Current Input Capacitance 5 5 1.5 0.7 V V A pF Input Between GND and VDD.
Rev. 1.01
9
XRD9855/9856 XRD98L55/98L56
DC ELECTRICAL CHARACTERISTICS - XRD98L55 and XRD98L56 (CONT'D) Unless otherwise specified: DVDD = VDD = 2.7V, Pixel Rate = 18MSPS, VRT = 2.07V, VRB = 0.27V
Symbol Parameter Min. Typ. Max. Unit Conditions
Digital I/O Timing TDL TPW1 TPW2 TPIX T BK TVD TRST TSC TSET Latency Data Valid Delay Pulse Width of SHD Pulse Width of SHD Pixel Period Sample Black Aperture Delay 10 10 37 56 7 28 35 ns ns ns ns ns VDD = 2.7V to 3.6V, Temperature -40C to 85C range Sample Video Aperture Delay 6 ns VDD = 2.7V to 3.6V, Temperature -40C to 85C range RSTCCD Switch Delay 0 5 ns VDD = 2.7V to 3.6V, Temperature -40C to 85C range Shift Clock Period Shift Register Setup Time Pipeline Delay 50 10 4 100 ns ns cycles
Power Supplies VDD DVDD IDD IDD27 IDDPD Analog Supply Voltage Digital Output Supply Voltage Supply Current Supply Current @ 27MHz Power Down Supply Current 2.7 2.7 3.0 3.0 40 45 50 3.6 3.6 55 65 100 V V mA mA A DVDD < VDD Always DVDD = VDD = 3.0 V (XRD9855) FS = 27MHz (XRD9856) STBY1 = 0 and STBY2 = 0
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3 VDD to GND VRT & VRB VIN All Inputs All Outputs Storage Temperature +7.0V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V -65C to 150C Lead Temperature (Soldering 10 seconds) 300C Maximum Junction Temperature 150C Package Power Dissipation Ratings (TA= +70C) qJA = 54C/W TQFP ESD 2000V
Notes: 1 Stresses above those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. 3V DD refers to AVDD and DVDD. GND refers to AGND and DGND.
Rev. 1.01
10
XRD9855/9856 XRD98L55/98L56
SYSTEM DESCRIPTION Correlated Double Sample/Hold (CDS) & Programmable Gain Amplifier (PGA); Gain [7:0] The function of the CDS block, shown in Figure 2, is to sense the voltage difference between the black level and video level for each pixel. The CDS and PGA are fully differential. The PGA output is converted to a single ended signal, and then fed to the ADC. IN_POS (CDS non-inverting input) should be connected, via a capacitor, to the CCD "Common" voltage. This is typically the CCD Reference output or ground. IN_NEG (CDS inverting input) should be connected, via a capacitor, to the CCD output signal. During the black reference phase of each pixel the SDRK switches are turned on, shorting the PGA1 inputs to VDD. The sampling edge of SHP turns off the SDRK switches, sampling the black reference voltage on capacitors C1 & C2. During the video phase of each pixel the SPIX switches are turned on. The difference between the pixel reference level and video level is transmitted through capacitors C1 & C2 and converted to a fully differential signal by the differential amplifier PGA1. The sampling edge of SHD turns off the SPIX switches, sampling the pixel value on capacitors C3 & C4.
CDS
VDD External Coupling Capacitors CCD Supply CCD Signal
PGA
Gain Register
SDRK RSTCCD In_Pos C1 In_Neg
SPIX + PGA1 C2 C3 CLAMP Offset Calibration VBIAS~0.8 ADC Code Enable Cal C4 PGA2 BUF to ADC
Figure 2. Block Diagram of the CDS & PGA
Rev. 1.01
11
XRD9855/9856 XRD98L55/98L56
CCD
RSTCCD SHP SHD (Internal Signals) SDRK SPIX PGA1 Output PGA2 Output ADCLK Hold Track
Figure 3. Timing Diagram of the CDS Clocks and Internal Signals, CLK_POL = 1, M2=0
PGA1 provides gains of 0dB, 8dB & 16dB (1x, 2.5x, and 6.25x). The gain transitions occur at PGA gain codes 64d and 128d (40h & 80h). PGA2 provides gain from 6dB to 22dB (2x to 12.5x) with 0.125dB steps. Figure 4 shows the measured PGA gain vs. Gain Code. The combined PGA blocks provide a programmable gain range of 32dB. The minimum gain (code 00h) is 6dB. The maximum gain (code FFh) is 38dB. The following equation can be used to compute PGA gain from the gain code:
40 35 FS = 18MHz VDD = 3.0V VRT = 2.3V VRB = 0.3V TA = 25C
PGA Gain [dB]
30 25 20 15 10 5
code Gain[dB] = 6 + 32 x 256
where code is between 0 and 255. Due to device mismatch the gain steps at codes 6364 and 127-128 may not be monotonic.
0
0
64
128 Gain Code
192
256
Figure 4. PGA Gain vs. Gain Code
Rev. 1.01
12
XRD9855/9856 XRD98L55/98L56
Analog-to-Digital Converter The analog-to-digital converter is based upon a twostep sub-ranging flash converter architecture with a built in track and hold input stage. The ADC conversion is controlled by an internally generated signal, ADCLK (see Figure 3). The ADC tracks the output of the CDS/ PGA while ADCLK is high and holds when ADCLK is low. This allows maximum time for the CDS/PGA output to settle to its final value before being sampled. The conversion is then performed and the parallel output is updated, after a 2.5 cycle pipeline delay, on the rising edge of RSTCCD. The pipeline delay of the entire XRD9855/XRD9856 is 4 clock cycles. The internal reference values are set by a resistor divider between VDD and GND. To enable the internal reference, connect VRTO to VRT and connect VRBO to VRB. To maximize the performance of the XRD9855/ XRD9856, the internal references should be used and decoupled to GND. Although the internal references have been set to maximize the performance of the CDS/PGA channel, some applications may require other reference values. To use external references, drive the VRT pin directly with the desired voltage. Connect VRB to VRBO. Do not drive VRB directly. The ADC parallel output bus is equipped with a high impedance capability, controlled by OE. The outputs are enabled when OE is low. Automatic Offset Calibration, Offset [7:0] To get the maximum color resolution and dynamic range, this part uses a digital controlled offset calibration system to compensate for external offset in the CCD signal as well as internal offsets of the CDS, PGA and ADC. The calibration is performed every frame when the CCD outputs the Optical Black pixels, please see the section on Frame Timing. The Calibration logic compares the ADC output to the value stored in the serial port offset register, and increments or decrements the offset adjust DAC to make the ADC code equal to the code in the offset register. The first adjustment requires 8 pixels, then 6 pixels for subsequent adjustments. The offset register is 8 bits wide. Two MSBs set to 00 are added when compared to the 10-bit ADC code. After power-up the part may require up to 264 adjustments to converge on the proper offset. These adjustments can be made over many lines or frames. For example, with 20 optical black pixels per line, the calibration will make 3 adjustments per line, and initial convergence will require at most 88 lines.
Graph 1.
XRD9855 Typical Vdrk (CCD Offset) Calibration Range @ 25C
Rev. 1.01
13
XRD9855/9856 XRD98L55/98L56
CDS IN_NEG
PGA
ADC
Reg
IN_POS
10 DB[9:0]
XOE
Offset Adjust DAC
Up/Down Counter
A A-B B
Reg
Offset Reg
Enable
EnableCal
State Machine
ADCLOCK
Figure 5. Automatic Offset Calibration Loop
Manual Global Offset, V [1:0] In some systems the black level offset can be larger than the Automatic Offset Calibration Range. The XRD9855/XRD9856 provide a user programmable global offset adjustment which adds to the automatic offset calibration. The global offset is applied at the PGA input, so it's input referred value does not change with PGA gain code, see Figure 6. The magnitude of the global offset is controlled by bits V[1:0] in the mode register. (See Table 1.)
CCD Input
CDS
+
PGA
ADC
DB[9:0]
V[1:0] Manual Global Offset
Automatic Offset Calibration
Figure 6. Manual Global Offset & Automatic Offset Calibration Serial Interface
V[1] 0 0 1 1
V[0] 0 1 0 1
Offset 0mV 25mV (default) 50mV 75mV
Table 1. Manual Global Offset Programming
A three wire serial interface, (LOAD, SCLK, and SDI), is used to program the PGA gain register, the Calibration offset register, the Mode control register, and the Aperture delay register. The shift register is 10 bits long. The first two bits loaded are the address bits that determine which of the four registers to update. The following eight bits are the data bits (MSB first, LSB last). When LOAD is high SCLK is internally disabled. Since SCLK is gated by LOAD, SCLK can be a continuously running clock signal, but this will increase system noise. To enable the shift register the LOAD pin must be pulled low. The data at SDI is strobed into the shift register on the rising edges of SCLK. When the LOAD signal goes high the data bits will be written to the register selected by the address bits (see Figure 7).
Rev. 1.01
14
XRD9855/9856 XRD98L55/98L56
ADDRESS (MSB) SDI AD1 AD0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 DATA (LSB) Bit 0
TSET=10ns min. SCLK
Data Shifts on Rising Edges
TSC=50ns min. TSET=10ns min. LOAD TSET=10ns min. Load Internal Register
Figure 7. Serial Port Timing Diagram
Address Name Gain Offset Mode Delay AD1 0 0 1 1 AD0 0 1 0 1 bit 7 Gain[7] Offset[7] V[1] Dp[2] bit 6 Gain[6] Offset[6] V[0] Dp[1] bit 5 Gain[5] Offset[5] M3 Dp[0] bit 4 Gain[4] Offset[4] M2 Dd[2] Data bit 3 Gain[3] Offset[3] Test3 Dd[1] bit 2 Gain[2] Offset[2] Test2 Dd[0] bit 1 Gain[1] Offset[1] M1 Dr[1] bit 0 Gain[0] Offset[0] Reset Dr[0]
Table 2. Serial Interface Register Address Map
bit 7
bit 6
bit 5
bit 4
bit 3 Gain [7:0]
bit 2
bit 1
bit 0
0 0 0 0 0 0 0 0 - minimum gain (6dB) * 1 1 1 1 1 1 1 1 - maximum gain (38 dB)
Table 3. Gain Register Bit Assignment
bit 7
bit 6
bit 5
bit 4 bit 3 Offset [7:0]
bit 2
bit 1
bit 0
0 0 0 0 0 0 0 0 - do not use 0 0 0 0 0 0 0 1 - do not use 0 0 0 0 0 0 1 0 - minimum offset code 0 0 0 0 1 0 0 0 - default offset code, typical offset code 00100000 0 0 1 1 1 1 1 1 - maximum offset code
Table 4. Offset Register Bit Assignment
Rev. 1.01
15
XRD9855/9856 XRD98L55/98L56
bit 7 V[1:0]
0 0 - 0mV offset 0 1 - 25mV offset* 1 0 - 50mV offset 1 1 - 75mV offset
bit 6
bit 5 M3
0 - Clamp only* 1 - Clamp & Cal
bit 4 M2
0 - RSTCCD* 1 - no RSTCCD
bit 3 Test3
0 - TestVin off* 1 - TestVin on
bit 2 Test2
0 - test off* 1 - factory test
bit 1 M1
0 - auto detect* 1 - manual
bit 0 Reset
0 - normal* 1 - reset
Table 5. Mode Register Bit Assignment
bit 7
bit 6 Dp[2:0] 0 0 0 - SHP min delay * 1 1 1 - SHP max delay
bit 5
bit 4
bit 3 bit 2 Dd[2:0] 0 0 0 - SHD min delay * 1 1 1 - SHD max delay
bit 0 Dr[1:0] 0 0 - RSTCCD min delay * 1 1 - RSTCCD max delay
bit 1
Table 6. Delay Register Bit Assignment
Note: * Indicates default value
SHP, SHD and RSTCCD Signals, M2 = 0 The SHP input to the XRD9855/XRD9856 determines when the Black level of each pixel is sampled. For CLK_POL=high timing mode, the black level is sampled on the falling edge of SHP. For CLK_POL=low timing mode, the black level is sampled on the rising edge of SHP. The sampling edge of SHP should be positioned so that it samples the pixel black level at a stable and repeatable point. The black level should be sampled after the CCD output has had time to settle from the reset pulse and before the output transitions to the video level (see Figure 8). Aperture delay TBK needs to be taken into consideration when positioning the sampling edge of SHP (see Figure 8). This aperture delay is the time from the sampling edge of SHP to the time the pixel black level is actually sampled by the CDS. The correct positioning of SHP will be 6-7 ns prior to where the black level has adequately settled. This is typically just before the CCD signal starts the transition to the video level. The SHD input to the XRD9855/XRD9856 determines when the Video level of each pixel is sampled. For CLK_POL=high timing mode, the video level is sampled on the falling edge of SHD. For CLK_POL=low timing mode, the video level is sampled on the rising edge of SHD.
Rev. 1.01
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The sampling edge of SHD should be positioned so that it samples the pixel video level at a stable and repeatable point. The video level should be sampled after the CCD output has settled from the black level and before the output transitions to the reset pulse. Aperture delay TVD needs to be taken into consideration when positioning the sampling edge of SHD (see Figure 8). This aperture delay is the time from the sampling edge of SHD to the time the pixel video level is actually sampled by the CDS. The correct positioning of SHD will be 5-6 ns prior to where the video level has adequately settled. RSTCCD is intended to overlap the reset pulse of each pixel. This is intended to eliminate the reset pulse transients from getting into the CDS circuitry. Positioning of the RSTCCD signal so that it overlaps the CCD signal reset pulse is not always practical due to the timing generators being used or the frequency at which the CCD is running. The most critical thing to remember for RSTCCD is that it can not be high when sampling either the black level or video level.
Reset Pulse RSTCCD Switch Turn Off
RSTCCD Switch Turn On TBK T VD Pixel Video Level Pixel Black Level Sample Point Sample Point
CCD Signal T RST
RSTCCD
SHP
SHD
Figure 8. CDS Timing Diagram (CLK_POL = 1, M2 = 0)
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Pixel N CCD Signal Sample Pixel Black Level Sample Pixel Video Level
SHP
SHD
RSTCCD TDL DB[9:0] (Output) Data N-4 Data N-3 Data N-2 Data N-1 Data N
Figure 9. Conversion Timing Diagram Showing Pipeline Delay (CLK_POL = 1, M2 = 0)
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CDS Clock Polarity The CLK_POL pin is used to determine the polarity of the CDS clocks (SHD, SHP, CLAMP). See Figures 10 & 11, and Tables 7 & 8.
Event RSTCCD RSTCCD SHP SHD SHP/SHD Action Disconnect CDS Inputs from Reset Noise Connect CDS Inputs and Track Black Level Hold Black Level and Track Video Level Hold Video Level No Action Event RSTCCD RSTCCD SHP SHD SHP/SHD Clamp Low High Action Disconnect CDS Inputs from Reset Noise Connect CDS Inputs and Track Black Level Hold Black Level and Track Video Level Hold Video Level No Action Activate DC Restore Clamp
Clamp High Activate DC Restore Clamp Enable_Cal Activate Offset Calibration High
Enable_Cal Activate Offset Calibration
Table 7. Timing Event Description Table Valid for CLK_POL=1, M2=0
Table 8. Timing Event Description Table Valid for CLK_POL=0, M2=0
Line N Active Video pixels on OB*pixels OB LINES CCD Signal EnableCal Clamp RSTCCD SHP SHD
Line N+1 Vertical Shift Dummy & OB*pixels Active Video pixels on OB LINES
* Note: OB = Optically Black or Shielded pixels.
Figure 10. CCD Line Timing, CLK_POL= 1, M2 = 0
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Line N Active Video Pixels on Optical Black Lines OB* Pixels Vertical Shift
Line N+1 Dummy & OB* Pixels Active Video Pixels on OB line
CCD Signal EnableCal Clamp RSTCCD SHP SHD CLK_POL=Low * Note: OB = Optically Black or Shielded pixels.
Figure 11. CCD Line Timing with CLK_POL = 0, M2 = 0 No RSTCCD Pulse Timing, M2 = 1 To help simplify the timing required to drive the XRD9855/XRD9856 we have included a timing mode which does not require an active signal for RSTCCD. To use this timing, bit M2 in the timing mode register must be set high. In this timing mode, RSTCCD must be kept low. No changes are required for the timing of the SHP and SHD signals. The polarity of SHP, SHD and Clamp are still controlled by the CLK_POL pin. The digital outputs change on the sampling edge of SHD (see Figure 12). This mode can be used with both the XRD4460 and XRD9853 compatible timing as described in the Line Timing section. Data output DB[9:0} is delayed as SHD is delayed with the delay feature AD[1:0] = [1,1].
CCD Signal
Pixel N
RSTCCD
1 0 1 0 1 0 1 0 Data N-4 Data N-3 Data N-2 Data N-1 Data N
SHP
SHD
DB[9:0]
Figure 12. Timing for no RSTCCD Pulse, M2=1 & CLK_POL=1, RSTCCD=0
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Programmable Aperture Delays Dp[2:0], Dd[2:0], Dr[1:0] To help fine tune the pixel timing, the XRD9855/ XRD9856 allows the system to adjust the aperture delays associated with SHP (TBK), SHD (TVD) and RSTCCD (TRST) by programming the Aperture Delay serial port register. On power up these three aperture delays are set to their minimum values. The SHP aperture delay is set by bits Dp[2:0]. Each LSB adds approximately 2ns of delay. The SHD aperture delay is set by bits Dd[2:0]. Each LSB adds approximately 2ns of delay. The RSTCCD aperture delay is set by bits Dr[1:0]. Each LSB adds approximately 4ns of delay.
Dr[1] 0 0 1 1 Dr[0] 0 1 0 1 RSTCCD Aperture Delay TRST (typ) 3ns (default) 7ns 11ns 15ns
Table 11. Programmable RSTCCD Delays
Line Timing with Frame Calibration At the beginning and/or end of every CCD frame there are a number of Optical black lines. The XRD9855/ XRD9856 uses the output from these pixels for the DC Restore Clamp and Black Level Offset Calibration functions. These functions are controlled by the Clamp and/or EnableCal pins. The XRD9855/XRD9856 is designed to be compatible with the Clamp Only timing of the XRD4460 or the Clamp & EnableCal timing of the XRD9853. On power up the chip will automatically detect which timing is being used and make the necessary internal adjustments. If EnableCal is high when Clamp is active, then "Clamp Only" timing is selected (M3=0). If EnableCal is low when Clamp is active, then "Clamp & Cal" timing is selected (M3=1). If required, the automatic detection function can be disabled through the serial port, and the chip can be forced into one of the two timing modes by programming mode register bits M3 & M1. Frame clibration however, can only be used with m3=0. To maximize dynamic range in the dark areas of an image the PGA black level output must be equal to the bottom reference voltage of the ADC. This ensures that a dark pixel input corresponds to a desired minimum code output from the XRD9855 and XRD9856. The XRD9855 and XRD9856 use the Optically Black (OB) pixels on a CCD array to calibrate for itself and the CCD. Figure 13 shows the outline of a typical CCD. The shaded region on the outside of the array indicates the position of the optically black (OB) pixels. The center region indicates the position of the active pixels used for an image.
Dp[2] 0 0 0 0 1 1 1 1
Dp[1] 0 0 1 1 0 0 1 1
Dp[0] 0 1 0 1 0 1 0 1
SHP Aperture Delay TBK (typ) 6ns (default) 8ns 10ns 12ns 14ns 16ns 18ns 20ns
Table 9. Programmable SHP Delays
Dd[2] 0 0 0 0 1 1 1 1
Dd[1] 0 0 1 1 0 0 1 1
Dd[0] 0 1 0 1 0 1 0 1
SHD Aperture Delay TVD (typ) 5ns (default) 7ns 9ns 11ns 13ns 15ns 17ns 19ns
Table 10. Programmable SHD Delays
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Optically Black Pixels (OB) Active Pixels
The XRD9855 and XRD9856 use a digital feedback loop to achieve auto-calibration. The output of the ADC and a desired dark code programmed in the offset register are compared during the OB pixel output from the CCD. The recommended offset register value is 32 decimal. The difference determines whether the offset adjustment DAC increments or decrements. This adjusts the offset of the PGA to achieve the desired ADC output code for a dark pixel input. The first adjustment requires 8 cycles of SHP/SHD clocks but every subsequent adjustment requires only 6 cycles: 1 cycle for CDS, 3 cycles for A/D conversion, 1 cycle for logic, and 1 cycle for DAC update, see Figure 14. When Enable_Cal pin is low, the offset calibration logic is disabled, and the current state of the offset DAC is held constant.
N+1 N
Figure 13.
Typical Outline of an Area Array CCD.
The CCD has many OB pixels available for use in calibration. Some are available at the start and end of each line while whole lines of OB pixels are available at the top and bottom of the array. The XRD9855 and XRD9856 take advantage of the large number of OB pixels available at the top and bottom of the CCD array to perform calibration before any active pixels are processed.
The XRD9855 and XRD9856 calibration time depends on the calibration method and the number of OB pixels available. The time required to achieve calibration, in frame calibration, depends on the number of OB pixels present in each line. Using Frame calibration, calibration can be achieved after several lines depending upon the number of OB pixels at the top or bottom of an array. Enable_Cal must be generated by the timing generator to properly frame the optical black lines.
OB Pixels INNEG RSTCCD SHP SHD Enable_Cal
ADC Sample point ADC Sample point 5 6 7 2 3 4 5 6 7 0 RESET
State
0 RESET
1 Enable Cal on settle
2
3
4
CDS ADC ADC ADC Digcomp/ DAC CDS ADC ADC ADC Digcomp/ DAC samples converts converts converts accum Update samples converts converts converts accum Update input input
Figure 14. XRD9855 and XRD9856 Offset Calibration Timing, M3 = 1
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Frame calibration uses the OB lines available at the start and end of the array, see the dark shaded regions at the top and bottom of Figure 15, to perform its autocalibration. The dark shaded regions of Figure 15 are the OB lines at the start and end of the CCD array. Typically, these OB lines are the largest blocks of OB pixels available on the array. Using these areas will allow the XRD9855 and XRD9856 to achieve calibration before any active pixels are processed. This means that the XRD9855 and XRD9856 can achieve calibration for the very first frame if OB lines are used for calibration at the start of the array.
Active Pixels
The timing needed for Frame Calibration Mode is shown in Figure 16. In Frame Calibration Mode, Enable_Cal needs to be active during the OB line output from the CCD. Enable_Cal gates the XRD9855 and XRD9856's auto-calibration logic and must never be high when CLAMP is active. Clamp still needs to be active once a line, either during start of line or end of line OB pixels. Frame calibration is useful for applications where fast calibration is needed. With frame calibration, the XRD9855 and XRD9856 can achieve calibration before the first frame is started.
Frame Calibration (OB) Pixels
Optically Black (OB) Pixels
N+1 N
Frame Calibration (OB) Pixels
Figure 15. OB Lines Used For Frame Calibration on a Typical CCD Array
Line N Active Video pixels on OB*pixels OB LINES CCD Signal EnableCal Clamp RSTCCD SHP SHD
* Note: OB = Optically Black or Shielded pixels.
Line N+1 Vertical Shift Dummy & OB*pixels Active Video pixels on OB LINES
Figure 16. Frame Calibration Mode Timing, CLK_POL= High
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Clamp Only Timing (XRD4460 compatible) M1=1, M3=0, NOT RECOMMENDED In this mode EnableCal is held high, and Clamp is activated during the Optical Black pixels. While this mode is available, it is not recommended for best performance. This timing does not perform frame calibration. The Clamp signal is used to trigger a one-shot which controls the internal DC restore switch and the calibration logic. The DC restore switch is turned on for two pixels after Clamp is activated. Then the Calibration logic is enabled and runs until Clamp is deactivated. The chip can be forced into this timing mode by programming the Mode control register bits M1=1 and M3=0.
Line N+1 Dummy & OB* Pixels Signal Pixels
Line N
Optical Black Line CCD Signal EnableCal 1 0 Clamp 1 0 Internal DC 1 Restore Switch 0 Internal Calibrate 1 0 1 RSTCCD 0 SHP 1 0 SHD 1 0
Vertical Shift
(Horizontal Clocking Off)
Minimum 10 OB Pixels
2 OB Pixels
* Note: OB = Optically Black or Shielded pixels.
Figure 17. Clamp Only Line Timing CLK_POL=1, EnableCal=1, M1=1, M3=0, M2=0
Clamp Only Mode
CCD Input CDS PGA ADC DB[9:0]
DC Restore Switch Bias Clk_Pol Clamp EnableCal Control Logic
Offset Calibration
Figure 18. Clamp Only Mode (XRD4460 Compatible) M1=1, M3=0
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XRD9855/9856 XRD98L55/98L56
Clamp & EnableCal Timing (XRD9853 Compatible) M1=1, M3=1 In this mode EnableCal must be active during the large number of Optical Black pixels (usually at the end of each CCD line or at the start of a frame), Clamp should be active during the Dummy pixels (usually at the beginning of each CCD line). The EnableCal pin (always active high) directly controls the calibration logic. The Clamp pin (polarity determined by CLK_POL) controls only the DC restore switch at the CDS input. EnableCal and Clamp must not be active at the same time. Clamp must be used every line. The chip can be forced into this timing mode by programming the Mode control register bits M1=1 and M3=1.
Line N
Line N+1
Signal Pixels
OB* Pixels
Vertical Shift
(Horizontal Clocking Off)
Dummy & OB Pixels
Signal Pixels
CCD Signal EnableCal Clamp Min. 2 Pixels RSTCCD SHP SHD * Note: OB = Optically Black or Shielded Pixels.
Min. 8 OB Pixels
Figure 19. Clamp & EnableCal Timing, CLK_POL=1, M1=1, M3=1, M2=0
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Clamp & EnableCal Mode CCD Input CDS PGA ADC DB[9:0]
DC Restore switch bias Clk_Pol Clamp EnableCal
Offset Calibration
Figure 20. Clamp & Enable Cal Mode (XRD9853 Compatible), M1=1, M3=3
Stand-by Mode (Power Down) The STBY1 and STBY2 pins are used to put the chip into the Stand-by or Power down mode. In this mode all sampling and conversion stops, The digital outputs are put into the high impedance mode, and the power supply current will drop to less than 50A. For most applications STBY1 and STBY2 should be connected together and treated as a single control pin. If an application uses the TestVin pin to access the PGA output or the ADC input then STBY1 and STBY2 must be separately controlled, see the truth table below.
STBY2 0 1 0 1
STBY1 0 0 1 1
CDS/ PGA Off On Off On
ADC Off Off On On
Clock Inputs Off On On On
Digital Outputs High-z High-z On On
Table 12. Stand-by Truth Table
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Chip Reset The chip has an Internal Power-On-Reset function to ensure all internal control registers start up in a known state. Pulling the Reset pin high or writing a logic 1 to the Mode Registers reset bit will also reset the chip to the Power-up default conditions.
Register Gain[7:0] OS[7:0] V[1:0] M3 M2 M1 Test3 Test2 Reset Dp[2:0] Dd[2:0] Dr[1:0] Default 00000000 00001000 01 0 0 0 0 0 0 000 000 00 Notes minimum gain code 08 hex 25 mV offset Clamp only RSTCCD required Automatic timing detect On Test modes off Test modes off reset bit will reset itself minimum delay minimum delay minimum delay
Table 13. Reset Conditions
Using TestVin (Pin 20) The TestVin pin allows access to the input of the ADC, or it can be used to monitor the CDS/PGA output. The TestVin pin accesses the ADC input node through switch S1 (see Figure 18). This switch is controlled by Bit3 of the serial port Test register. When the TEST3 bit of the mode register is high, switch S1 is "ON" and the TestVin pin can be used to access the ADC input/ PGA output. When the TEST3 bit of the mode register is low, switch S1 is "OFF" and the TestVin pin is disconnected from the ADC input/PGA output.
To use TestVin as an auxiliary ADC input force STBY2=low and STBY1=high. This will disable the CDS/PGA and leave the ADC operating. If M2=0, the ADC clock is generated from RSTCCD and SHP (See Figure 19). If M2=1, the ADC clock is generated from SHP & SHD (See Figure 20).
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TestVin
S1 CDS PGA ADC
Figure 21. Using TestVin to Access PGA Output & ADC Input
Mode Reg. TestVin Normal
AD1 1 1
AD0 0 0
V[1] 0 0
V[0] 0 0
M3 0 0
M2 1 1
Test3 1 0
Test2 0 0
M1 0 0
Reset 0 0
Table 14. Serial Port Data to Use TestVin
CCD Signal
CCD Signal
RSTCCD
RSTCCD
SHP
SHP
SHD
SHD
ADC Clock (internal)
Track
Hold
ADC Clock (Internal)
Track
Hold
ADC Data
ADC Data
Figure 22. ADC Clock Generation, CLK_POL=1, M2=0
Figure 23. ADC Clock Generation, CLK_POL=1, M2=1
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Digital Output Power Supplies The DVDD and DGND pins supply power to the digital output drivers for pins DB[9:0], UNDER, and OVER. DVDD is isolated from VDD so it can be at a voltage level less than or equal to VDD. This allows the digital outputs to interface with advanced digital ASICs requiring reduced supply voltages. For example VDD can be 5.0 or 3.3V, while DVDD is 2.5V. Power Supply Sequencing There are no power supply sequencing issues if DVDD and VDD of the XRD9855/XRD9856 are driven from the same supply. When DVDD and VDD are driven separately, VDD must come up at the same time or before DVDD, and go down at the same time or after DVDD. If the power supply sequencing in this case is not followed, then damage may occur to the product due to current flow through the source-body junction diodes between DVDD and VDD. An external diode (50822235) layed out close to the converter from DVDD to VDD prevents damage from occurring when power is cycled incorrectly. Note: VDD must be greater than or equal to DVDD or the source-body diodes will be forward based.
VDD
DVDD
Source-Body Junction Diode Between DVDD & VDD Output Register Digital Output Source-Body Junction Diode Between DGND & GND
GND
DGND
Figure 24. DVDD & DGND Digital Output Power Supplies, VDD > DVDD
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General Power Supply and Board Design Issues All of the GND pins, including DGND, should be connected directly to the analog ground plane under the XRD9855/XRD9856. The VDD's should be supplied from a low noise, well filtered regulator which derives the power supply voltage from the CCD power supply. All of the VDD pins are analog power supplies and should be locally decoupled to the nearest GND pin with a 0.1F, high frequency capacitor. DVDD is the power supply for the digital outputs and should be locally decoupled. DVDD should be connected to the same power supply network as the digital ASIC which receives data from the XRD9855/XRD9856. In general, all traces leading to the XRD9855/XRD9856 should be as short as possible to minimize signal crosstalk and high frequency digital signals from feeding into sensitive analog inputs. The two CCD inputs, In_Pos and In_Neg, should be routed as fully differential signals and should be shielded and matched. Efforts should be made to minimize the board leakage currents on In_Pos and In_Neg since these nodes are AC coupled from the CCD to the XRD9855/XRD9856. The digital output traces should be as short as possible to minimize the capacitive loading on the output drivers (see Figure 25)
12V 5V/3V Regulator VDD In_Neg CCD In_Pos GND DGND DGN D DB[9:0] DVDD DVDD Digital ASIC 5V/3V Regulator
XRD9855/XRD9856 AGND AGND
Figure 25. XRD9855/XRD9856 Power Supply Connections
Application Note
If increasing the PGA Gain to code 128 (80h) or higher causes a larger than expected offset increase in the ADC digital output codes, the problem may be due to the limited Automatic Offest Calibration range. This problem may be solved by increasing the Global Offset code, V[1:0], in the Mode Register. The default is V[1:0] = 01 (binary). Try increasing to V[1:0] = 10, or V[1:0] = 11.
For additional information on the XRD9855 feaures: - Auto-detect - EnableCal & Clamp Line Timing - Clamp Only Line Timing - Digital Clibration Loop - Dark Voltage Calibration Range Please see Application Notes XRDAN109, XRDAN110, XRDAN112, XRDAN113 and XRDAN114.
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to CCD VDD Signal
to CCD Ground
0.01F
Serial Interface
0.01F
0.1 F
36 35 34
GND 33
32
31
30
29
VRT 28
0.01F
27
26
In_Pos
LOAD
37
In_Neg
VRBO
VRTO
VDD
VRB
SDI
NC
CLAMP SHD SHP RSTCCD GND CLK_POL VDD SYNC UNDER DB0 DB1
SCLK 24 RESET 23 STBY2 22 STBY1 21 Test 20 GND 19 from Clock Signal Generator VDD
From Clock Signal Generator
38 39 40 41
0.1 F VDD
42 43 44 45 46 47 48
XRD9855/XRD9856
EnableCal 18 VDD 17 OE 16 OVER 15 DB9 14
NC
25
0.1 F VDD
DGND
DVDD
DB2
DB3
DB4
DB5
DB6
DB7
NC
NC
NC
DB8 13
10
11
NC
Digital Data Bus
Figure 26. XRD9855/XRD9856 Application Schematic CLK_POL=0
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DVDD
0.1F
12
1
2
3
4
5
6
7
8
9
NC
XRD9855/9856 XRD98L55/98L56
2.4 2.2 2.0 1.8 1.6 en, mV RMS 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 32 64 96 128 GAIN CODES 160 192 224 255
25MHz 27MHz
AVDD = DVDD = 5.0V VRT = AVDD/1.3
30MHz
VRB = AVDD/10 MODE = NON-RSTCCD
18MHz
12MHz
Figure 27. Input Reference Noise vs. PGA Gain Codes
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XRD98L55 INPUT REFERRED NOISE
2.0 AVDD = DVDD = 3.0V 1.8 1.6 1.4
30MHz
VRT = A VDD/1.3 VRB = AVDD/10 MODE = NON-RSTCCD
1.2 en, mVRMS
25MHz
1.0 0.8
27MHz
18MHz
0.6
12MHz
0.4 0.2 0.0 0 32 64 96 128 GAIN CODES 160 192 224 255
Figure 28. XRD98L55 Input Referred Noise
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48 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.4 mm TQFP) rev. 2.00
D D1 36 25
37
24
D1
D
48
13
1 B A2 e
1 2
C A Seating Plane A1 L
SYMBOL A A1 A2 B C D D1 e L a
INCHES MIN MAX 0.055 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.004 0.008 0.346 0.362 0.272 0.280 0.020 BSC 0.018 0.030 0x 7x
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.09 0.20 8.80 9.20 6.90 7.10 0.50 BSC 0.45 0.75 0x 7x
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NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation Datasheet July 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.01
35
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